1. Field of the Invention
The present invention generally relates to a float gate memory device, and more specifically, to a nano scale float gate memory device having an improved retention characteristic and cell integrated capacity obtained by depositing a plurality of float gate cell arrays vertically with a plurality of cell insulating layers.
2. Description of the Related Art
FIG. 1 is a cross-sectional diagram illustrating a memory cell of a conventional float gate memory device.
A memory cell of the conventional float gate memory device comprises a N-type drain region 4 and a N-type source region 6 which are formed in a P-type substrate 2, a first insulating layer 8, a float gate 10, a second insulating layer 12 and a word line 14 which are sequentially formed on the channel region.
In the above-described memory cell of the convention float gate memory device, a channel resistance of the memory cell is differentiated by a state of charges stored in the float gate 10.
That is, since positive channel charges are induced to the channel when electrons are stored in the float gate 10, the memory cell becomes at a high resistance state to be turned off.
Meanwhile, negative channel charges are induced to the channel when positive holes are stored in the float gate 10, so that the memory cell becomes at a low resistance state to be turned on.
In this way, data are written in the memory cell by selecting kinds of charges of the float gate 10, so that the memory cell can be operated as a nonvolatile memory cell.
However, since the retention characteristic is degraded when the size of the memory cell of the conventional float gate memory device becomes smaller, it is difficult to perform a normal operation.
Specifically, since the retention characteristic of the memory cell having a float gate structure of a nano scale level becomes weaker even in a low voltage stress, a random voltage cannot be applied to a word line in a read mode.